The present invention relates to manufacturing IC components suited for signals within the radio frequency range and manufactured using bipolar technology based on silicon (Si), in particular for simultaneously manufacturing vertical NPN-transistors, capacitors and lateral PNP-transistors on a silicon substrate and for producing deep substrate contacts.
Nowadays it is possible to produce fast bipolar circuits having a high packing density by using bipolar transistors (Bip-transistors) which are manufactured having two layers of polysilicon and thus are transistors of the so called double poly-Si-type, using self-aligning or self-aligning technology combined with electrical isolation provided by trenches surrounding the transistor, so called trench isolation. A schematic cross-sectional view of such a previously known trench isolated bipolar transistor of xe2x80x9cdouble poly-Si-typexe2x80x9d, which is manufactured using self-aligning technology, is shown in FIG. 1.
In the known manufacturing process for bipolar transistors of double poly-Si-type one lets the first deposited polysilicon layer form a base connection. If the transistor is NPN-type, this poly-Si-layer is doped strongly to type P. The last deposited polysilicon layer, which is doped strongly to type N and forms an emitter electrode, is physically separated from the first deposited polysilicon layer forming the base connection by an underlying electrically isolating layer and isolating side-strings, also called xe2x80x9cspacersxe2x80x9d. The advantage of the self-aligning method when manufacturing bipolar transistors is that both the base resistance and the capacitance between base and collector are reduced. Furthermore, the introduction of isolation provided by trenches drastically reduces the capacitance between collector and substrate. Thereby, circuit performances are considerably improved.
Hereinafter, a frequently used, known way of manufacturing a trench-isolated bipolar transistor of NPN-type will be described in detail with reference to FIGS. 2 to 6, which schematically show the production method. As a base material a monocrystalline silicon substrate 101 of type P is used having its surface located in a (100)-plane of the silicon crystal structure, see FIG. 2. The bottom diffusion 102 which is a so called xe2x80x9cburied layerxe2x80x9d and which can be constituted of for example an ion implanted layer of arsenic or antimony, is lithographically defined, after which an epitaxial silicon layer 103 having a thickness of about a couple of xcexcm is applied to the plate 101. Thereafter N- and P-areas are defined on the plate 101 using lithography combined with ion implantation. The N-areas 104, which are produced by ion implantation using e.g. phosphorous, are placed directly above the bottom diffusion 102 of type N+. Other areas 105, which are located between the N-areas 104, are P-doped and are manufactured by e.g. ion implantation of boron, see FIG. 2.
Then the active areas are defined by means of conventional LOCOS-methods (xe2x80x9cLOCal Oxidation of Siliconxe2x80x9d), see J. A. Appel et al., xe2x80x9cLocal oxidation of silicon and its application in semiconductor technologyxe2x80x9d, Philips Research Report, Vol. 25, 1970, pp. 118-132. Then first an isolating mask 106 of a suitable material is applied, see FIG. 3, which is then lithographically patterned. After that silicon 107 is thermally grown in the apertures in the mask 106, so that a base area 108 and a collector area 109 for the transistor to be produced remain and are formed within the areas, where the mask covers the surface. After thus having defined the active areas, separated by an oxide layer area 109xe2x80x2, and having removed the mask layer 106, isolating trenches 110 are lithographically defined, the windows in the trench etching mask, not shown, being placed at the boundary line between the N-type epitaxial areas 104 and the P-type epitaxial areas, whereafter the thermally grown silicon oxide material 107 and the substrate material 101 are etched away in said windows using isotropic dry etching, until the trenches 110 have acquired a desired depth, about 5 to 10 xcexcm, and extend down into the non-affected P-substrate 101.
The walls of the trenches 110 are then thermally oxidized, so that a thin, electrically isolating layer, not shown, is obtained, after which the trenches are filled with an isolating or semi-isolating material 111, for example silicon oxide or polycrystalline silicon, also called poly-Si or polysilicon. The filling material is then etched away by dry etching until a flat surface is obtained. Then the surface of the plate is oxidized and in particular the silicon material in the openings of the trenches 110 is oxidized in the case where the trenches have been filled polysilicon, in order to obtain an isolating layer, not shown, at the surface of the openings. If the trenches 110 are already, from the start, filled with only oxide, no such extra oxidizing step is required. The result is shown in FIG. 3. It can be observed that the extension of the base area 108 in FIG. 3 is defined using LOCOS-methods according to the discussion above. The drawback of this method will be discussed later, among other things in conjunction with a description of a modified process for manufacturing a transistor.
After forming the trenches 110 a collector plug 112 is lithographically defined, see FIG. 4, i.e. a low resistance connection between the surface of the component plate and the bottom diffusion 102, within the collector area 109. After that a dopant is applied, usually phosphorous, by ion implanting in the lithographically defined openings.
The description of the continued manufacturing process will be made for the above mentioned NPN-transistor of double poly-Si-type having a self-aligned base-emitter junction, since this component type is usually combined with electrical isolation obtained by trenches.
After the definition of active areas 108, 109, see FIG. 2, and forming a collector plug 112 as described above, a thin layer 113 of polysilicon is deposited having a thickness of some hundreds of nm, see FIG. 4. The polysilicon layer 113 is then doped to become type P+ by ion implanting boron, after which a thin silicon oxide layer 114 is deposited on top of the polysilicon layer by means of CVD (xe2x80x9cChemical Vapour Depositionxe2x80x9d). This polysilicon layer of type P+ doped with boron will after the finished manufacture form a so called extrinsic base 113xe2x80x2 or base connection or base terminal by the diffusion of dopant into the surface layer of the N-epitaxial area 104 directly under the polysilicon layer 113. The oxide layer 114 produced by CVD and the polysilicon layer 113 located thereunder are lithographically patterned in order to define an emitter opening 115 located within the base area 108. Thereafter those portions of these two layers are removed, which are not covered by the lithographic mask, not shown, by a dry etching method such as plasma etching. After patterning the emitter opening 115 a thin thermal oxide 116 is grown for protecting the surface in the emitter opening, whereafter a so called intrinsic base, indicated by the crosses 117, is produced by ion implanting boron. The intrinsic base 117 is thus located precisely in and beneath the emitter opening 115.
In order to separate the emitter to be produced from the extrinsic base xe2x80x9cspacersxe2x80x9d or side strings 118 are formed along the sides of the emitter opening 115, see FIG. 5. This is made by first depositing an oxide layer by CVD conformally over the plate, after which an anisotropic dry etching procedure is used to etch away this oxide layer on the flat surface portions of the plate. Thereby a side string or spacer 118 of CVD oxide is formed along those steps which are formed when making the patterning for producing the emitter opening 115. After forming such spacers 118 a thin polysilicon layer 119 is deposited having a thickness of some hundreds of nm on the surface of the plate. This layer is implanted with arsenic in order to become type N+ and will after annealing form the emitter electrode 120 of the transistor. After patterning and etching the N+ polysilicon layer 119 in order to produce the emitter electrode the structure obtains the configuration shown in FIG. 5. Usually, one lets areas of this upper polysilicon layer 119 doped to N+, which thus forms the emitter electrode, also remain on top of the collector area 109, see also FIG. 3, and the collector plug 112, where it serves as a collector terminal 121.
The circuit is then passivated by a layer 122 of for example silicon oxide, see FIG. 6, in which contact holes 123, 124, 125 to the base, emitter and collector of the transistor are lithographically defined. After etching the contact holes the circuit is coated with a metal layer 126 by sputtering for example aluminum, which penetrates into the contact holes 123, 124, 125 and will form electrical contacts for connection to the exterior. The conductor layer 126 is then defined by lithography and etching in order to produce exterior terminals 127, 128, 129 and the final result appears from FIG. 6, compare also FIG. 1. FIG. 1 is a better picture of the final component, even if also there the thicknesses of the layers in certain cases are exaggerated.
As appears from the description above, the base area 108 is defined by means of the LOCOS-methods, see FIG. 3. Then preferably a two layer structure is used consisting of silicon dioxide, which is located directly on top of monocrystalline silicon, and silicon nitride as a local oxidation mask when thermally growing the so called field oxide 107. When making the field oxidation some lateral diffusion of oxygen will occur along the boundary layer between monocrystalline silicon and silicon oxide, and then some growth of oxide also occurs under the margin of the nitride layer, see 130 in FIG. 3. This oxide 130 is popularly called a xe2x80x9cbirds-beakxe2x80x9d. Thereby the extension of the base area will be only to some extent defined by the lithographically defined nitride-oxide-mask structure. One can say that the accuracy of the area is defined by the remaining xe2x80x9cbirds-beakxe2x80x9d after finished manufacture. In order to compensate for lacking accuracy and process variations when producing these xe2x80x9cbirds-beaksxe2x80x9d the base area 108 is made unnecessary large. Thereby, an unnecessary large capacitance between the base and the collector is obtained.
Furthermore, when producing the field oxide 107 in the N-area 104 a concentration 131 of dopant, a so called xe2x80x9cdopant pile upxe2x80x9d, will occur in the boundary layer between the field oxide 107 and the surface of the monocrystalline silicon substrate 101, see FIG. 3. When then the polysilicon layer 113 of type P+, which forms the extrinsic base, is made to come in contact with the base area 108 outside the side strings 118, it results in an increased capacitance between the base and the collector in the finished NPN-transistor, see FIGS. 3 and 4.
A basic type of vertical transistor is e.g. disclosed in U.S. Pat. No. 3,246,214 for F. B. Hugle. Vertical transistors using field oxide for defining active regions are disclosed in the published European Patent Application 0 375 323 for Texas Instruments (Brighton et al.) and the published Japanese Patent Application 95-245313 (Application No. 94-32764).
When manufacturing a transistor to be a part of electronic circuits on a semiconductor chip, there may also be a need for other components, e.g. passive components such as capacitors, inductors and resistors, to be included in the circuits. When manufacturing such a complicated device as a high frequency transistor of the general type described above many processing steps are required and then it may be advantageous if some of the processing steps can be employed to produce such other devices, and it will be in particular be advantageous if no extra processing steps at all are required, i.e. generally if some kind or kinds of passive components can be integrated in the same process flow requiring as few extra additional processing steps as possible. In the published Japanese Patent Application 90-27550 (Application No. 71-75779) is disclosed how a capacitor and a vertical transistor are simultaneously manufactured at the surface of a substrate. However, the capacitor can have a considerable series resistance resulting in losses owing to the resistance of the electrical connection to a bottom capacitor electrode located under the dielectric layer.
The production of the electrically isolating side-strings, also called xe2x80x9cspacersxe2x80x9d, mentioned above, serving to electrically isolate the active region from connection structures made of a layer of highly doped silicon such as polysilicon are for example described in the published European Patent Application 0 303 435 for Sony Corp. (Hiroyoki Miwa), U.S. Pat. No. 5,037,768 for Cosentino and U.S. Pat. No. 5,541,124 for Hiroyoki Miwa et al. The spacers have, using the conventional manufacturing methods using anisotropic etching in a single step, some width in the horizontal direction along the surface of the transistor to be produced which can be unnecessary large and perhaps also somewhat badly defined. If possible, this isolating structure should thus be replaced by some structure made of a better defined, thinner isolating layer.
Polysilicon conductors in transistors arranged for electrically connection to active layers are disclosed in U.S. Pat. No. 5,037,768 for Cosentino et al. (vertical transistor) and U.S. Pat. No. 5,302,538 for Ishikawa et al. (field effect transistor).
Electrically isolated component areas at a surface of a substrate of an integrated circuit are disclosed in U.S. Pat. No. 4,958,213 for Eklund et al. P-wells can be used for isolating N-wells from each other, the N-wells having highly doped buried regions under them and the N-wells having buried doped regions doped to a lower level. However, the electrical isolation provided in this way can in some cases be unsatisfactory, in particular for applications involving high radio frequencies. Deep substrate connections can be used for connecting portions of a substrate which are substantially unaffected by layers of components and isolating devices to ground when the integrated circuit is used are disclosed in the published British Patent Application 2 291 257 for International Rectifier Co. (C. C. Choi et al.). However, such substrate connections can also appear to operate in an unsatisfactory way for high frequency radio applications.
It is an object of the present invention to solve the problems mentioned above and thus to provide semiconductor components, in particular bipolar transistors, having higher performance, in particular a bipolar NPN-transistor having a reduced capacitance between its base and collector and a bipolar lateral PNP-transistor having a reduced capacitance between its emitter and collector.
It is another object of the invention to provide such a solution to the problems presented above, that a substrate capacitor, i.e. a passive capacitor component located at the surface of the substrate, is formed at the same time as the capacitance between the base and the collector in a bipolar NPN-transistor is reduced.
It is another object of the invention to provide a substrate capacitor which can be formed at the same time as a bipolar NPN-transistor is produced and which has low losses and occupies a small surface area.
It is another object of the invention to provide shallow and deep substrate contacts for electrically isolating component areas at the surface of a substrate.
It is another object of the invention to provide a transistor structure having field oxide regions which are left intact and not unnecessarily eroded in the dry etching step.
It is another object of the invention to provide a transistor structure having electrically connecting silicide only at desired places.
It is another object of the invention to provide an integrated circuit including components such as transistors, which has component areas which are efficiently electrically isolated from each other, in particular in lateral directions along the surface of the integrated circuit.
It is another object of the invention to provide an efficient substrate connection for an integrated circuit including components such as transistor.
It is another object of the invention to provide a transistor, generally a bipolar device, isolated by a trench or trenches, in which the trench or trenches can be produced in an efficient way.
In order to produce an NPN-transistor thus a laminated layer of silicon oxide and silicon nitride is introduced which is located on top of the active area (collector area) of the NPN-transistor. The laminate is lithographically patterned, so that the base area of the transistor is defined by an opening in the laminated layer. At the same time a lateral PNP-transistor can be produced using lithographically defined openings in order to produce the emitter and collector of this transistor.
It will thereby also be possible to form a substrate capacitor, which uses the silicon nitride layer as a dielectric, without any extra mask step, at the same time as the capacitance between the base and collector of the bipolar NPN-transistor is reduced.
A semiconductor component, which can be a bipolar transistor of type NPN, has an active area at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active area is partly covered by an electrically isolating surface layer, preferably including a nitride layer. A base area in the active area is determined by a well defined opening lithographically produced in the electrically isolating surface layer. In the case where the semiconductor component, which in this case can be a bipolar transistor of PNP-type, instead has emitter and collector areas, which at the surface of the component are surrounded, as seen along the surface of the component, by such thick field oxide areas, an emitter area and/or a collector area can in the corresponding way be determined by a lithographically defined opening in an electrically isolating surface layer. By the lithographic definition in these two cases the electrically isolating surface layer will extend over and beyond surrounding field oxide areas, so that a strip of the electrically isolating surface layer exists between the base area and between the emitter or collector area, respectively, and the field oxide areas located closest to this area.
The electrically isolating surface layer includes advantageously a laminate of silicon nitride at the top and thereunder silicon oxide. The silicon nitride layer is advantageously used as an efficient dielectric in a simultaneously produced capacitor resulting in small area occupied by the capacitor. This capacitor will then be located at the surface of the substrate and comprises a dielectric layer covering a portion of the surface of a doped or low-doped region of the substrate doped to a first doping level. An electrically conducting layer is arranged over the dielectric layer and forms a capacitor electrode. An electrically conducting connection extends to a region under the dielectric layer from a surface of a portion of the substrate which is not covered by the dielectric layer. Furthermore, the dielectric layer is arranged over a buried, highly doped region doped to a second doping level significantly higher than the first doping level. A contact plug having a high doping doped to a third doping level, the third doping level being significantly higher than the first doping level, extends from a portion of the surface of the substrate, which is not covered by the dielectric layer, down the buried region. Such a connection of the bottom capacitor electrode formed by the material directly under the dielectric layer will have a low series resistance and the capacitor will have small losses.
An electrode plug having a high doping doped to substantially the third doping level for forming a bottom electrode of the capacitor can extend from the under side of the dielectric layer down to the buried region. For such an electrode plug, the first doping level can be very small and even substantially correspond to a substantially intrinsic semiconducting material. Using such an electrode, which is produced at the same time as the connection to the buried layer from the surface, will still more reduce the losses of the capacitor.
In the bipolar, a side-string structure is used at an active area, at which area electrically conducting silicon material is arranged in contact with a border region at the active area. By means of a process comprising materials having different etching characteristics an electrically isolating layer conformally arranged substantially only on vertical surface portions of the electrically conducting silicon portions can be obtained. The electrically isolating layer then has everywhere substantially the same or a uniform thickness. An electrically isolating oxide layer different from the electrically isolating layer is then preferably arranged at substantially the whole surface of the electrically conducting silicon material and under the electrically isolating layer, which advantageously is a silicon nitride layer.
When making such a side-string structure, which can generally be said to be a process of producing a free area at a surface of a substrate, the free area being defined by edges of an electrically isolating layer, the following steps can be executed:
Applying a material layer to the surface over and above a first area having edges, which first area is intended to form the free area. The material layer can be a layer of electrically conducting material, e.g. doped silicon such as highly doped polysilicon serving as a base connection. This conducting layer is then at least at portions close to the first area in electrical contact with the surface of the substrate;
Applying conformally a first silicon oxide layer over the material layer;
Making an opening through the first oxide layer and through the material layer down to the surface of the substrate. The opening is made somewhat larger or a little larger than the first area and has substantially vertical edges defining it, so that the substantially vertical edges of the opening have a substantially constant distance to the edges of the first area;
Applying conformally an electrically isolating layer over all of the surface. This electrically isolating layer must be different from the first oxide layer or being another type than the first oxide layer. It can preferably be a silicon nitride layer;
Applying conformally a second oxide layer having etching characteristics different from etching characteristics of the first oxide layer over all of the electrically isolating layer;
Making a first anisotropic etching for removing the second oxide layer only at substantially all flat, horizontal surfaces. Then the electrically isolating layer will be is exposed on substantially all of the flat, horizontal surfaces and xe2x80x9cdisposablexe2x80x9d side-strings of the general triangular shape and made up of the second oxide layer will then remain on vertical surfaces;
Making a second etching for removing the electrically isolating layer only at surfaces which are not covered by the second oxide layer, the electrically isolating layer then being removed substantially only on flat, horizontal surfaces;
Making a third etching, using the fact that the second oxide layer has etching characteristics different from the etching characteristics of the first oxide layer, for removing only remaining portions of the second oxide layer without substantially attacking free surface portions of the first oxide layer, whereby portions of the electrically isolating layer remain substantially only on vertical edge surfaces of the material layer and the first oxide layer surrounding the first area.
The side-string structure as described above and produced by this method may be advantageous since the opening in the material layer, typically a highly doped polysilicon layer, will be only very little narrowed since the electrically isolating layer can be made very thin.
The process can also be said to comprise first conformally applying a first electrically isolating layer over the surface of the substrate and then conformally applying a second electrically isolating layer over the first electrically isolating layer. The materials of the first electrically isolating layer and the second electrically isolating layer must be selected to have etching characteristics which are different from each other. Finally selective etchings are made for first removing the second electrically isolating layer and the first electrically isolating layer everywhere except on substantially vertical surface portions and for then removing the first electrically isolating layer also on the substantially vertical surface portions. The first etching can preferably be made in two steps comprising first a first substep, in which only the second electrically isolating layer is removed only on horizontal surface portions and then a second substep, in which the first electrically isolating layer is removed only on horizontal surface portions.
In a process for among other purposes avoiding unnecessary silicidizing a transistor is thus generally produced at the surface of a substrate. An electrically conducting silicon layer such as a doped polysilicon layer is produced on top of the surface for electrical contact with doped regions in the surface and then an electrically isolating layer of preferably silicon oxide is applied directly on top of the electrically conducting silicon layer. Thereafter an additional electrically conducting layer, also usually of electrically conducting silicon such is a polysilicon, is applied directly on top of the electrically isolating layer. Finally the electrically isolating layer is removed within regions, which are not covered by the additional electrically conducting layer, in order that an electrical contact will be attained therewith from later applied electrically conducting metal layers. When removing the electrically isolating layer, it is removed only within selected regions and then at least one selected region is smaller than a region not covered by the additional electrically conducting layer.
When removing only the selected regions of the electrically isolating region, a mask can be used, in which openings are lithographically made to produce remaining portions of the mask. The remaining portions of the mask are arranged to cover selected first regions of formerly applied electrically isolating layers and also second regions, at which a silicidation is to be avoided in a later applying of electrically conducting metal layers. Then the first regions and the second regions, after removing the electrically isolating layer only within the selected regions, are still covered by the additional electrically isolating layer.
This procedure involving a patterning before removing the electrically isolating layer will protect earlier produced electrically isolating layers such as regions of field oxide. Also, the electrically isolating layer can be left on surface portions where a silicide is not desired.
In an integrated circuit of the general kind considered herein which comprises components at the surface of a substrate, an efficient electrical isolation between the components can be achieved by using P-wells and N-wells. Generally then, each component is produced substantially as built on a first region doped to a first doping type, preferably an N-well, and is located in the surface layer of the substrate. A first buried region is located directly under the first region and is highly doped to the first doping type. The integrated circuit further comprises second regions, such as P-wells, doped to a second doping type opposite the first doping type and arranged between the components in the surface layer of the substrate. Second buried regions are located directly under the second regions and have a moderate doping of the second doping type. They form electrical connections of the second regions to the substrate, the second regions electrically isolating the first regions and thereby the components from each other. In order to enhance the isolation an electrically well conducting layer is arranged on top of the second regions in the surface layer of the substrate and it is intended to be connected to electrical ground when using the integrated circuit. Enhanced doped regions may be located directly under the electrically well conducting layer in the second regions, the enhanced doped regions containing dopants which have diffused, during a suitable annealing process, out of the electrically well conducting layer for reducing the electrical resistance between the electrically well conducting layer and the second regions. Also, separate substrate connections may be arranged, preferably in the second regions. Such connections comprise a deep hole extend from the surface and end in the substrate under the second buried region which is located directly under the second region. The hole is filled with electrically conducting material such as a metal.
The contact of the electrically well conducting material in the deep substrate connections can be improved by making, before filling with electrically conducting material, a doping only at the bottom of the deep hole in order to reduce the resistance between the electrically conducting material and the substrate. The doping can be produced by implantation and annealing a dopant such as boron. After the doping at least one thin layer containing titanium be applied to walls and the bottom of the deep hole in order to increase the electrical contact.
Trenches can be used for isolating the components and can be produced in the conventional way by etching. Thereafter a laminated layer is applied to the walls of the trenches, the layer comprising at the bottom thermally grown silicon dioxide and thereon a thin silicon nitride layer, applied by deposition. Finally the remaining main portions of the trenches are filled by applying an electrically isolating or semi-isolating layer, such as a silicon oxide layer or a layer of undoped silicon, for example microcrystalline silicon, over the surface of the plate, for example by a suitable kind of deposition. The silicon nitride layer then acts as an etch stop in a subsequent planarizing etching for planarizing the layer, with which the main portions of the trenches are filled. Furthermore, if the material, which is used when filling the trenches, would have impurities, the silicon nitride layer prevents them from diffusing into the substrate material. Such a diffusion could reduce the electrically isolating function of the trenches.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.